Cadence Design Systems created the first unified TLM-driven design and verification solution. The methodology enables SoC designers to reap the benefits of transaction-level modeling (TLM). The TLM-driven solution improves productivity, design quality, and project schedule predictability. Unlike prior technology, Cadence’s solution allows customers to reuse TLM design and verification IP as golden source. The new solution enables SoC TLM IP to be designed, synthesized and verified, resulting in faster design creation, increased functional verification productivity, and more opportunities to reuse design and verification IP.
The Cadence TLM-driven design and verification methodology encompasses SystemC modeling guidelines for virtual platforms and high-level synthesis, and defines the process for performing multi-language OVM-based functional verification of TLM, TLM/RTL, and RTL. The methodology will be delivered in the form of manuals, self-paced tutorials, and workshops with hands-on labs. New solution capabilities include migration from C/C++ to enable automatic conversion of legacy design sources to SystemC TLM; high-level synthesis integrated with popular memory compilers to optimize for each architecture; and side-by-side analysis and traceability of SystemC and synthesized RTL.
The Cadence solution combines C-to-Silicon Compiler with new memory compiler integration and C/C++ usability, Incisive Enterprise Simulator with new TLM/RTL metric-driven verification and source level debug visualization, Calypto sequential logic equivalence checking, the first version of the TLM-driven design and verification methodology, and customer adoption services.
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