Altos Design Automation introduced Liberate MX ultra-fast, general purpose library characterizer for memories and custom macro blocks. Liberate MX generates instance specific library models in Liberty format including advanced current source models for timing and noise (CCS and ECSM). Liberate MX supports multiple fast-spice simulators including Synopsys CustomSim (HSIM, NanoSim and XA), Mentor Graphics ADiT, and Cadence Virtuoso UltraSim Full Chip Simulator for fast SPICE. Synopsys Hspice, Cadence Spectre, Mentor Graphics Eldo, and Altos Alspice are all supported for true-spice simulation. Liberate MX is available now. U.S. pricing starts at $120K for a 1 year license.
Liberate MX features automatic probing and dynamic partitioning to address the run-time, accuracy challenges that come with characterizing large macro blocks with millions of transistors. By utilizing vectors and a fast-spice simulator, Liberate MX is able to identify critical paths that can be condensed into dynamic partitions. The dynamic partitions can be accurately characterized using the same methods as standard cells using a true-spice simulator. This results in a dramatic improvement in both run-time (often 10X or more for large memories) and accuracy. Large 1Mbit memory instances have been fully characterized in less than a few hours on a single machine.
Liberate MX’s use of dynamic partitioning is able to account for effects common at advanced process nodes such as interconnect coupling and transistor stress. As dynamic partitions are smaller they can be simulated faster and/or with higher accuracy without overwhelming the true-spice simulator. Liberate MX does not rely on circuit pattern matching and hence can be used for a very wide range of circuit types from complex lower power SRAMs with power gating to custom blocks such as SERDES.
In addition to current source timing and noise models, Liberate MX generates pin capacitance, state-dependent leakage, and non-linear models for timing and power. Liberate MX can read input vectors or generate them from a high level truth table. The tool automatically identifies clock trees and latch nodes within the circuit to determine timing constraints reducing the onus on the engineer to manually specify measurement probes. The library models generated by Liberate MX are consistent with those created by Liberatetm for standard cells and I/Os which is essential for reliable electrical sign-off of System-on-Chip (SoC) designs.
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