RootCauseAnalyzer, from OneSpin Solutions, increases formal ABV productivity by making SystemVerilog assertion (SVA) and RTL design debug much easier and faster. RootCauseAnalyzer eliminates most of the time-consuming, error-prone manual analysis of complex information otherwise necessary to trace the root causes of assertion failures, speeding assertion, and design debug by up to 10x. The RootCauseAnalyzer is available in this month’s release of OneSpin’s 360 MV.
Displays diagnostic information to speed analysis of counterexamples that show the assertion failure.
An SVA code debugger that automatically pinpoints the failing parts of an assertion; it indicates where to start assertion debug, and identifies the signals and clock cycles involved in the failure. It provides source code value annotations for all assertion objects — including objects in referenced named sequences, and properties — during all relevant clock cycles of the counterexample. Thus it also enables efficient debugging of assertions that are described hierarchically to ease assertion coding, understanding and reuse.
Automates the tracing of signals involved in the assertion failure to related design signals, thus automating exploration of signal dependencies across clock cycles.
Marks the RTL source code regions involved in the assertion failure and automates exploration of these code regions across clock cycles, focusing and speeding RTL source code debug.
More info: OneSpin Solutions