RealTime Designer, from Oasys Design Systems, is a design tool for physical RTL synthesis of 100-million-gate designs. RealTime Designer synthesizes RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis. The tool features a RTL placement approach that eliminates unending design closure and iterations between synthesis and layout. RealTime Designer is immediately available and pricing begins at $395,000 for a one-year time-based license.
RealTime Designer follows a “Place First” methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.
Design teams must manually check for many results, such as design congestion, and send the design repeatedly through synthesis and layout. RealTime Designer is the first product to automate that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.
Synthesizing a physical block using TSMC 65nm – 700k instances, 70 Macros, running at 600MHz, and a “golden” floorplan – RealTime Designer completed the task in just 20 minutes and achieving design closure after a single iteration in place and route. In the traditional approach on the same design, a single iteration of synthesis took 14 hours. Furthermore, it took 6 months of iterations to achieve the best result of -300ps Worst Negative Slack, and in the end was not able to achieve design closure.
Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year. Output has been tested through all the popular place and route systems.
More info: Oasys Design Systems