Design Automation Conference Tutorials

The Design Automation Conference (DAC) will feature six educational, full-day tutorials focused on a variety of design methods. The tutorials will provide CAD professionals, design engineers, managers, and academic researchers with an in-depth look at electronic design. Tutorial attendees will have the opportunity to earn university Continuing Education Credits in the field of VLSI and Design Automation through a partnership with the University of California Santa Cruz (UCSC) Extension and the University of California San Diego (UCSD) Extension.

Design Automation Conference Tutorials

  • Low-Power SOC Design: State of the Art and Directions
    Monday, July 27: 8:30 am – 4:30 pm
    This tutorial will focus on industrial case studies that highlight state-of-the-art techniques to achieve improved energy efficiency, with special emphasis on aggressive scaling of the power supply. Practical challenges will be discussed, such as early power estimation at the architectural level, power verification along the design flow, timing characterization when using dynamic voltage/frequency scaling (DVFS) and power gating with retentive sequential elements.

  • High-Level Synthesis for ESL Design: Fundamentals and Case Studies
    Monday, July 27: 8:30 am – 4:30 pm
    Attendees participating in this tutorial will learn about High-Level Synthesis techniques they can use immediately. They will also examine the use and impact of High-Level Synthesis on the design process, from conception through implementation. At the conclusion of the tutorial, attendees also will have gained insight into the long-term direction the industry will take.

  • Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon
    Friday, July 31: 9 am – 5 pm
    This tutorial will address state-of-the-art methods for detecting and correcting bugs after the first few silicon prototypes of a design become available. It is intended for microprocessor architects and designers, verification engineers, and CAD professionals interested in a better understanding of current post-silicon validation technologies. It will also benefit designers and verification experts in providing an overview of runtime verification solutions that have recently been proposed by the research community.

  • CAD: Utilizing the State of the Art, and Beyond, in Parallel Programming
    Friday, July 31: 9 am – 5 pm
    Participants in this tutorial first will be introduced to the state-of-the-art in parallel programming and a number of the most commonly used languages will be introduced, including pThreads, OpenMP, Thread-Building Blocks and MPI. Later participants will be given an overview of the state-of-the-art in applying these technologies to CAD.

  • From Nanodevices to Nanosystems: Promises and Challenges of IC Design with Nanomaterials
    Friday, July 31: 9 am – 5 pm
    This tutorial will focus on nanoscale devices and will address major existing nanosystems design principles and identify the key challenges and solutions for bridging the gap between nanodevice research and nanosystem building. The tutorial will conclude with insights for attendees regarding future nanoscale device and nanoscale system research.

  • Functional Verification Planning and Management: Navigating from Specification to Functional Closure
    Friday, July 31: 9 am – 5 pm
    This tutorial will teach state-of-the-art methods for planning, monitoring and assessing verification progress, each an essential step for achieving predictable, successful verification. Attendees will discuss how to choose design features that are candidates for verification using each of these techniques so that the overall verification labor is minimized while verification completeness is maximized.

More info: Design Automation Conference (DAC)