Si2 Design for Manufacturability Workshop

The Silicon Integration Initiative (Si2) will host the Design for Manufacturability Workshop — DFM Challenges at Sub-45nm Design at the Design Automation Conference (DAC). The free workshop will be held 1PM – 3PM on July 27 in Room 130 at the Moscone Convention Center in San Francisco, CA. The workshop will describe the current situation in the DFM arena and present tangible and specific progress in a number of design areas targeted at 45nm and below. The Si2 event will present interface standards being developed between chip design and manufacturing flows.

The DAC workshop will showcase the tangible progress that is being made. It will demonstrate how companies may adopt the results and participate in their continued evolution. As part of the workshop, selected vendors will present their products and techniques aimed at helping designers produce higher yielding integrated circuits and systems at advanced process nodes. Comparisons of restricted 2D layouts, prescriptive 1D layouts and methods for the integrated analysis and layout optimization will be presented for process nodes from 45nm down to 22nm. The construction methods, analysis views and the objective functions for multi-goal optimization will be presented by several companies who are enabling high volume production of circuits at 32nm and are now staking out plans for moving down to 22nm.

The Design for Manufacturability Workshop will also offer a clear lexicon that defines manufacturing technology parameters for foundries, EDA vendors, and end customers. This includes establishing a clear DFM Terminology and the infrastructure roadmap for standard interfaces between design and manufacturing.


  • Jim Culp – IBM
  • Greg Hackney – Mentor Graphics
  • Qi De Qian – IC Scope Research
  • Mike Smayling – Tela Innovations
  • Vivek Singh – Intel

More info: Silicon Integration Initiative (Si2)