The Catapult C Synthesis 2009a release, from Mentor Graphics, features support for control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS). The enhancement enables designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. The Catapult C Synthesis tool automatically generates control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed. The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000.
Catapult C Synthesis 2009a Features
- Support for control-logic synthesis from pure C++
- Decoupling Control Channel (DCC) technology
- Accuracy for control units
- Abstraction for algorithmic blocks
- New patent-pending verification and debug flow
- Fully automated multi-level clock-gating
- Dynamic power management interfaces
- Reduces power consumption by an average 40%
The 2009a release of Catapult C Synthesis tool unifies control logic synthesis and algorithmic synthesis, which traditionally been addressed using different languages, formalisms and abstractions. Now engineers can describe control logic along with algorithmic behavior in a single and coherent model leveraging standard ANSI C++. Catapult C Synthesis 2009a release features a new synthesizable C++ construct, which enables designers to easily specify asynchronous data communication, allowing full control over concurrent hardware creation. The algorithmic representations driven by the dataflow with control-dominated blocks synchronized by clocks. The result is a coding style familiar to hardware designers, letting users easily express communication, priority and task coordination within an abstract representation of concurrency. The new approach formalizes a modeling style, which provides the necessary accuracy for control oriented tasks, while preserving the abstraction beneficial for algorithmic subsystems.
The Catapult C Synthesis tool automates multi-level clock gating and interfacing to dynamic power and clock management units. The Catapult C tool will analyze deep cones of logic to find gateable clocks. The optimization delivers near 100% perfect clock gating by operating at the flop level, maximizing power savings by locally inferring the gating logic surrounding the targeted registers. Catapult C Synthesis tool also exports real-time information on the state of all system blocks. This information is relayed to power management units leveraging dynamic frequency and voltage scaling heuristics to achieve system-wide power savings.
More info: Mentor Graphics