Sonics MemMax DRAM System

The Sonics MemMax DRAM System is a pre-configured, verified, and silicon-proven IP block that can be integrated into a variety of SoCs quickly and easily. The IP block is a combination of Sonics’ advanced memory scheduler and Synopsys’ DesignWare DDR Protocol Controller IP. The combination results in an IP block that is optimized for maximum DRAM access efficiency and scalability as designs move from DDR2 to DDR3. Based on Sonics’ proprietary scheduling technology, designers can experience up to 85% memory bandwidth utilization from the system through to the external DRAM memory. The MemMax DRAM System is available now from Sonics.

Sonics MemMax DRAM System

Sonics MemMax DRAM System Features

  • Thread-based scheduling maximizes overall DRAM efficiency and provides levels of quality of service for the different threads
  • MemMax groups reads and writes based upon rank address to minimize timing delays caused by switching between banks of physical DRAM
  • Low-latency, High-Performance
  • Supports DDR2/3-Lite Protocol Controller (up to 1066MHz) and DDR3/2 Protocol Controller (up to 1600MHz)
  • System data flows are supported with different service qualities (best effort, allocated bandwidth, and priority)
  • QoS logic provides fine grain control of bandwidth rate setting
  • Contains basic data training logic for supporting DDR2/3-Lite and DDR2/DDR PHYs
  • MemMax arranges requests to avoid events that interfere with a smooth, pipelined flow of operations in the DRAM
  • Scheduler requests are issued to the controller in a short, configurable DRAM block size that is typically set to match the DRAM burst length
  • To increase efficiency, the scheduler employs the largest OCP burst size up to the configured DRAM block size
  • The user can choose the sizes of the buffers, modes of operation, QoS settings that best suit his application
  • MemMax Scheduler can trade-off high memory utilization, with low latency requirements
  • Provides a single vendor DDR2/DDR3 interface solution, when combined with the DesignWare PHY IP (available from Synopsys)
  • Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
  • Support for x8, x16, and x32 memories, for a total memory data path width of up to 72 bits
  • Support for up to four memory ranks and up to 32 open memory banks

The Sonics MemMax DRAM system leverages the low-latency, low gate count DesignWare DDR Protocol Controllers and the broad family of DDR PHYs to offer designers a comprehensive solution for memory subsystems, from the system interconnect through to the DDR SDRAMs. The efficiencies in the MemMax DRAM System make it easy to design SoCs because many features are already integrated and tested. This improves time-to-market because designers needn’t waste time tuning the memory.

More info: MemMax DRAM Systems