The Solve Well Proximity, from Solido Design Automation, is an application that analyzes and solves well proximity effect problems that become major concerns at 90 nm and below. Solve Well Proximity application enables semiconductor designers to avoid heuristics-based conservative guard-banding or multiple iterations between circuit and layout. Designers are able to proactively address well proximity effects during the circuit-design stage without area sacrifices or increased design time resulting from other approaches. The Solve Well Proximity application is now available for use with the Variation Designer platform.
Well proximity effects occur because, during the CMOS manufacturing process, atoms can scatter laterally from the edge of the photoresist mask and become embedded in the silicon surface near the edges of the retrograde wells needed for latch-up protection and suppression of lateral punch-through. This causes the MOSFET electrical characteristics to vary with the distance of the transistor from the well-edge. Traditionally, there have been two ways to deal with proximity effects. In one, because it is not known at the circuit design stage which devices are sensitive to the effects, the designer uses heuristics to conservatively guard-band devices. This results in area penalties. In the other approach, the circuit designer obtains post-layout extracted netlists and simulates to determine if there are any proximity effect-related issues. This is an iterative process and results in design time penalties.
The Solve Well Proximity application leverages foundry-provided well proximity parameters that are included in the SPICE model files but are not normally used due to the lack of appropriate tools at the circuit design stage. The new application is used by a chip designer during the circuit design stage to proactively account for well proximity effects. The designer can determine which devices are sensitive to proximity effects and by how much, and can obtain the appropriate proximity parameter values and minimum well distances. These values are back-annotated into the schematic and are then used by the layout engineer, reducing the silicon area occupied by excessive guard-banding and eliminating the time consumed by iterative post-layout simulations.
More info: Solido Design Automation