Synopsys and Semiconductor Manufacturing International Corporation (SMIC) introduced version 4.0 of their 65-nanometer (nm) RTL-to-GDSII reference design flow. The reference flow features support for the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology. The joint solution gives IC engineering teams a proven reference flow to advance SoC designs targeting SMIC’s 65nm process technology and Synopsys’ low power and DFM technologies. The SMIC-Synopsys Reference Flow 4.0 is available now.
The reference design flow was validated using SMIC’s in-house-developed CCS standard cell library, SRAM, PLL, IO Library, and low power cell library. The validation included multiple Vdd and multiple supply blocks with power-gating and data retention. Additional key features of the flow include multi-corner multi-mode (MCMM) optimization and critical area analysis and reduction, using IC Compiler, and design-for-test (DFT) synthesis combined with on-chip clocking control support for automatic generation of at-speed tests.
The flow utilizes Synopsys’ Galaxy Implementation Platform and offers designers with the ability to implement advanced low power techniques throughout the design flow including RTL synthesis and test, physical implementation, and signoff stages. In addition, IC Compiler’s Zroute technology supports SMIC’s 65nm routing rules using advanced routing algorithms to evaluate the impact of manufacturing rules, timing, and other design goals. The integration of Zroute balances design-for-manufacturing (DFM) optimization techniques with design timing, area, power and signal integrity goals for a particular chip design.