Calypto Design Systems introduced their PowerPro MG memory gating tool. PowerPro MG automatically generates power-optimized RTL by taking advantage of the low-power modes available in on-chip memories. The new tool features memory gating and eliminates costly and time-consuming manual coding. The memory gating tool runs on PC platforms running Linux. PowerPro MG is available now and is priced at $295K for a one year time based license.
With PowerPro MG, designers can apply sequential analysis techniques to automatically generate memory gating logic that significantly reduces both static and dynamic on-chip memory power. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours.
Calypto’s PowerPro MG reads in an RTL design written in VHDL or Verilog as well as the applicable memory models. Using Calypto’s patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible. PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. Aimed at large, complex SoC designs, PowerPro MG has been proven to reduce power consumption in a variety of end applications such as storage, networking, graphics and multimedia.
PowerPro MG works together with Calypto’s PowerPro CG (clock gating) product to produce the lowest power design possible. PowerPro CG reduces power by implementing sequential clock gating logic in the non-memory portions of an RTL design. Calypto’s SLEC product is used as part of a fully automated power optimization flow to comprehensively verify that the new power optimized RTL is functionally equivalent to the original RTL. Like PowerPro CG, the new PowerPro MG has no impact on the area or performance of a design.
More info: Calypto