PICO Extreme Power, from Synfora, is an algorithmic synthesis tool that automatically minimizes power consumption at the system-level based on a variety of techniques — including automatic multi-level clock gating insertion. Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy. PICO Extreme Power has delivered savings of up to 50% using this technique.
In traditional RTL (Register Transfer Language) design methodologies, inserting clock gating at a block level is usually a manual effort because it requires the knowledge of when the block is inactive. Using PICO Extreme Power, the designer uses directives to specify where to insert clock gating, and PICO does the rest automatically. As a result, PICO Extreme Power enables designers to retain all the productivity benefits of automated synthesis and verification — including reduced design and verification time and the ability to react very rapidly to changes in the design specification, while optimizing the IC power consumption.
The PICO Algorithmic Synthesis Platform provides productivity gains by creating application accelerators from an untimed C algorithm at the highest level of abstraction. PICO yields QoR (quality of results) that is competitive with manual design by using a unique parallelizing compiler and multi-level hierarchical abstraction and IP reuse. It offers the highest possible level abstraction for large designs, and has been proven to provide huge productivity gains on the largest production designs, not just on small blocks.
More info: Synfora