Synopsys created the System-Level Catalyst Program to accelerate the adoption of system-level design and verification. The program is open to electronic design automation (EDA) vendors, intellectual property (IP) vendors, embedded software companies and service providers. The Synopsys System-Level Catalyst Program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services. Members of the System-Level Catalyst Program gain access to Synopsys system-level and rapid prototyping products such as Innovator, DesignWare System-Level Library, System Studio, Synplify DSP and the Confirma platform. System-Level Catalyst Program members may also use the Synopsys System-Level Catalyst logo with their products or services to indicate system-level interoperability.
The purpose of the System-Level Catalyst Program is to promote interoperability between system-level design solutions. Making system-level model libraries and tools freely available to members as part of the Synopsys System-Level Catalyst program enables further mainstream adoption of ESL solutions. The System-Level Catalyst Program provides members tool access to validate and demonstrate interoperability or to support customers:
- IP Providers and EDA vendors get access to and support for Synopsys tool and library offerings to validate and demonstrate interoperability of system-level models of their IP and their tool solutions
- Embedded software vendors get access to Synopsys’ Innovator and DesignWare System-Level Library to validate and demonstrate interoperability of debuggers
- Qualifying embedded software developers who specialize in the development of drivers and software for Synopsys DesignWare Cores get access to virtual platforms and Confirma rapid prototyping platforms for software development prior to silicon availability
- Training and services companies can help system-level teams rapidly adopt the best practices for system-level design, virtual platforms, digital signal processing and FPGA based rapid prototyping
Founding members of the System-Level Catalyst program include: Agilent EEsof, Altera, ARC International, Carbon Design Systems, Cebatech, ChipVision Design Systems, Cofluent Design, CoWare, CriticalBlue, Doulos, Emsys, Enterpoint, Forte Design Systems, GreenSocs, IBM, Imperas, JEDA Technologies, Jungo, Lauterbach, MCCI, NoBug, SDV Ltd., Steepest Ascent, Synfora, Target Compiler, Tensilica, VaST Systems, and Xilinx.
More info: Synopsys System-Level Catalyst Program