SEMATECH Workshop on 3D Interconnect Metrology

SEMATECH will host a workshop dedicated to 3D Interconnect Metrology on July 15th in conjunction with SEMICON West in San Francisco, CA. The workshop will explore innovative metrology capabilities, share real metrology results from 3D interconnect processing, discuss metrology challenges, and define possible solutions for measuring films and high-aspect ratio features that dominate 3D architectures.

3D Interconnect Metrology Workshop Speakers

  • Metrology Applications of Enabling Technologies for Wafer Thinning, John Moore, Daetec
  • Scanning Acoustics Microscopy for Metrology of 3D Interconnect Bonded Wafers, James McKeon, Sonix
  • Through-Silicon Via (TSV) Processes Demand Macroscopic to Microscopic Metrology, Liam Cunnane, Metryx
  • 3D Interconnect Bonded Wafer Pair Metrology Using IR Microscopy, Richard Poplawski, Olympus-ITA
  • A Route Towards Non-Destructive Three-Dimensional CD Measurements of Through Silicon Via with X-ray Computed Tomography, Steve Wang, Xradia
  • Optical Metrology for TSV Process Control, Matthew Knowles, Zygo
  • Aspect Ratio Independent Non-Contact, High Throughput TSV Depth Metrology for 3D Interconnect Technology, David Marx, Tamar

The half-day workshop will conclude with a panel discussion entitled “3D Metrology – Does it Measure Up” that focuses on the readiness of metrology tools to support 3D integration challenges.

More info: SEMATECH Workshop on 3D Interconnect Metrology