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SystemRDL 1.0 Specification for IP Blocks

Posted by Ken Cheung in IP Cores,Models, Simulations on Monday, May 18, 2009

The SPIRIT Consortium released the SystemRDL specification. SystemRDL is a language for the design and delivery of registers to be used in IP blocks within electronic designs. The SystemRDL semantics support the entire life-cycle of registers from specification, model generation, and design verification to maintenance and documentation. Registers are not just limited to traditional configuration registers, but can also refer to register arrays and memories.

The SystemRDL language has been designed to increase productivity, quality, and reuse during the design and development of complex digital systems. It can and has been used to share IP within and between groups, companies, and consortiums. This is accomplished by specifying a single source for the register description from which all views, software, hardware, and documentation, can be automatically generated which ensures consistency between multiple views. A view is any output generated from the SystemRDL description, e.g., RTL code or documentation. These views include the production of IP-XACT descriptions. SystemRDL is used by many teams to succinctly capture a human readable and writable description from which the rest of the deliverables are produced.

The SPIRIT Consortium is a global non-profit organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design. It consists of EDA, IP, system integration, and semiconductor companies dedicated to the adoption of a unified set of specifications for configuring, integrating, and verifying IP in advanced SoC design tool sets.

More info: The SPIRIT Consortium SystemRDL v1.0 Standard

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