Takumi Technology has been issued a patent by the United States Patent and Trademark Office for its methods in system for simplifying layout processing. The patent (#7,487,490) covers technology in layout processing to enhance manufacturability of integrated circuits layouts for 65nm processes and below. Takumi Technology was previously issued five other patents in the areas of photolithographic mask correction and design for manufacturability.
As the gap between design and manufacturability in sub-wavelength technology widens, IC manufacturers are turning to optical resolution enhancement techniques such as optical proximity corrections in their design and manufacturing schema to produce features sizes of 65 nm or smaller. As the feature size decreases, distortion in the pattern transfer process becomes more severe forcing the design shapes to be modified such that the desired images can be printed on a wafer. These modifications account for the limitations in the optical lithography process as well as mask fabrication limitations and resist limitations.
Optical proximity correction on real design layouts is often handicapped by the existence of nuisance jogs that may be due to design rule or post-design processing. The existence of jogs or other imperfections increase the complexity of the original layout resulting in dramatic increase in the volume of data, which subsequently complicates layout processing. Jogs also force dissections at less-than-optimal locations, or simply miss dissection and correction when a jog is too small. This patent describes a simplified layout processing system that overcomes these limitations.
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