Cadence Design Systems and TSMC (Taiwan Semiconductor Manufacturing Company) introduced the Mixed Signal/Radio Frequency Reference Design Kit (MS/RF RDK). The RDK accelerate analog, mixed-signal, and RF designs and RF SoC verification and integration. The MS/RF RDK Initially targets 65nm process and was developed with Cadence Virtuoso mixed-signal technology. The TSMC 65nm MS/RF RDK is available now in limited release. General release to other customers will be in Q3 2009.
Mixed Signal/Radio Frequency Reference Design Kit
- Video tutorial
- Step-by-step design manual
- Complete PLL reference design database with schematics, layouts, and simulation test benches
- Design flow and methodology introduction
- Silicon test reports
- Release notes specifying design tool and version requirements
- TSMC 65nm process design kit (PDK)
The MS/RF RDK provides silicon-characterized behavioral models and a complete validated tutorial demonstrating an efficient MS/RF IC reference design flow that can help speed time to market. New technology includes a phase locked loop (PLL) noise-sensitive reference design example that can predict phase noise efficiently and accurately. Cadence technologies deployed include the Virtuoso custom design platform with SKILL-based Pcells, QRC Extraction, and Virtuoso Multi-Mode Simulation, which includes Spectre Circuit Simulator, Spectre RF and AMS Designer.
The new RDK helps resolve the long-standing challenge of full chip verification of SoCs with both analog, mixed signal and digital content. It enables a top-down MS/RF design methodology and a system-level simulation flow to reduce design cycle time and encourage IP reuse. The reference design in the RDK is an advanced Fractional-N Phase Locked Loop (PLL) developed in TSMC 65nm RF process technology and fully validated in silicon with accurate correlation between simulation results and silicon measurements.