ZeBu Supports SystemVerilog Assertions, Flexible Probes, Waveform Generation

EVE expanded the hardware debugging capabilities of ZeBu (for Zero Bugs) emulation systems. ZeBu now supports SystemVerilog Assertions, flexible probes, and complete access to all combinational signals at run-time for thorough design debugging. SystemVerilog Assertions, flexible probes, and simulated combinational signals are available now at no cost as add-on features to ZeBu.

Embedded and bound synthesizable SystemVerilog Assertions are supported in ZeBu emulation via EVE’s zFAST (ZeBu FAst SynThesis) tool. Synthesizable assertions can be compiled into the emulator with a scope at the design, module, instance and assertion level. Assertion failures, starts and ends, and successes can be reported live or via post-processing in any mode of operation for every assertion in the register transfer level (RTL) code.

The new flexible probes offer broad visibility into the design and improved performance. The maximum number for flexible probes is higher — more than 30,000 per field programmable gate array (FPGA) — than for static probes. Flexible probes don’t affect emulation performance when they are disabled. When enabled, they generate signal waveform files at the maximum speed offered by the fastest host PC hard disk without limiting the number of cycles or stopping the emulator. Because flexible probes are fully integrated into zRun and the ZeBu C++/C application programming interface (API), system-on-chip (SoC) designers can use them in any mode of operation.

Run-time signal access and dynamic probing in ZeBu have been enhanced with the addition of simulated combinational signals. The enhancement enables waveform generation of any RTL signal without adding extra logic into the design. Enhanced dynamic probes are integrated into the ZeBu run-time environment to generate a single waveform file and can be accessed interchangeably by software testbenches, providing improved debug capabilities.

More info: EVE ZeBu Debug