Formal Verification Patents for Jasper Design Automation

Jasper Design Automation has been granted four U.S. patents. The four new patents are:

  • 7,437,694
    Identification of certain RTL load signals and values, with their contribution to the proof target. This targeted information enables high performance and fast comprehension for formal users.
  • 7,421,668
    Meaningful visualization of properties independent of a circuit design under various conditions, which helps users debug any errors in how the property is implemented in a requirements model.
  • 7,418,678
    This invention provides methods for simplifying counters in a circuit design while preserving important implications, enabling reliable verification of circuit designs that use counters.
  • 7,412,674
    Applies the concept of analysis regions to analyze the properties/requirements for a design. This generates a visual display that is available to the user, representing source code in the analysis region for properties in comparison to the maximum possible analysis region.

More info: Jasper Design Automation