Cadence Design Systems released open source libraries for e and SystemC languages to support the Open Verification Methodology (OVM). Cadence has contributed these libraries to OVM. Cadence’s contribution enables the development of OVM-compliant verification components and testbenches in any of the three IEEE-standard languages used for verification and modeling: SystemVerilog, e, and SystemC.
The OVM multi-language new feature helps designers implement one methodology while continuing to deliver verification IP in each IEEE standard language required by our customers. The new open source OVM e and SystemC libraries introduced by Cadence will improve the design of verification environments.
The OVM was architected from the beginning with multi-language verification in mind. By using transaction-level modeling (TLM) channels as the basis for communication, OVM SystemVerilog verification components can communicate easily with existing e and SystemC components without changing those existing methodologies. The new libraries allow verification engineers to develop new components and testbenches in any of the three languages, using corresponding library elements with the same methodology and reuse guidelines.