Verification Methodology Manual for Low Power (VMM-LP) is a book about the industry best practices to accelerate the verification of low power designs. The methodology described in the VMM-LP book enables verification teams to attain coverage closure and pinpoint bugs using assertions. It can be implemented using voltage-aware static and dynamic verification tools, such as MVSIM with the VCS simulator and MVRC, which are part of the Eclypse low power solution from Synopsys. These tools are capable of checking low power designs for the rules documented in the VMM-LP book. The base classes will enable the infrastructure to create a structured and reusable verification environment based on the VMM-LP.
The VMM-LP book defines a robust and scalable verification architecture that can be used to quickly setup and complete verification of low power designs. The methodology addresses all aspects of functional verification of power management functions, including suggestions for static versus dynamic verification, design-for-verification techniques, and use of assertions and coverage metrics to achieve rapid verification closure.
The lead authors of the VMM-LP book are Srikanth Jadcherla, group director of Research and Development at Synopsys and founder of ArchPro Design Automation, Inc.; Janick Bergeron, Synopsys Fellow and moderator of the Verification Guild web site; Yoshio Inoue, chief engineer, Design Technology Division, Renesas Technology Corp.; and David Flynn, ARM fellow and co-author of the Low Power Methodology Manual (LPMM).