CoWare SystemC Model for Rambus XDR Memory Architecture

CoWare and Rambus have teamed together on an ESL design environment with CoWare Platform Architect for Rambus’ XDR memory architecture. CoWare will distribute a SystemC model with the flexibility to match configurations of Rambus’ XDR memory subsystems. SystemC model designed for Rambus’ XDR memory architecture is available immediately from CoWare as part of the CoWare Model Library.

Design engineers can now use CoWare Platform Architect ESL environment to do full architectural exploration, design verification, and software performance validation when designing with an XDR memory subsystem. This solution provides a huge productivity boost for the design of high-performance systems by accelerating the design process as well as enabling parallel development of the hardware and software.

Rambus’ XDR memory architecture transaction level model incorporates the XDR memory controller, memory controller interface (PHY), and XDR DRAM devices capable of delivering speeds of 3.2 to 4.8Gbps. The SystemC models allow thorough system performance analysis of various options for end applications, design configurations, and device types.

More information: CoWare | Rambus