OVP CPU Models Support SystemC TLM-2.0 and 1,000 MIPS
Open Virtual Platforms announced OSCI SystemC transaction level modeling (TLM)-2.0 support for all the OVP fast models. This enables all OVP models, including the certified processor models, to work in SystemC TLM2.0 platforms. Previously, OVP processor models had been available for use in OVP-based virtual platforms only. This release of OVP tools includes the OVPsim simulator and a native OSCI TLM-2.0 interface. OVP processor models in a SystemC TLM-2.0 simulation run benchmarks such as Peakspeed at 500-1,000 million instructions per second. The models were developed by Imperas and are free to download and use now.
All OVP CPU models now work with TLM-2.0 and include ARM, OpenCores OR1K, MIPS Technologies’ MIPS32 4K, 24K and 34K core families, and the ARC 600 and 700 families. Models and example bare metal platforms are available as open source, along with examples of each model being used in a SystemC TLM-2.0 platform.
One of OSCI TLM-2.0′s value proposition is that it makes the development of fast virtual platforms for software development easier to achieve. The alignment of OVP with the TLM-2.0 standard helps address one of the critical requirements for the successful deployment of virtual platforms, which is the ready availability of processor models.
With TLM-2.0, OSCI has made significant strides in interoperability, enabling models from different vendors to work together in a virtual platform. In addition, features such as the Direct Memory Interface (DMI) have increased performance many times over, making TLM-2.0 a viable option for software virtual platforms.
More information: OVP | Imperas
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