DesignCon IP Summit
The International Engineering Consortium’s (IEC) announced IP Summit will be a featured program at the DesignCon conference and exhibition. The IP Summit will address the role of semiconductor IP in electronic design through featured speakers, panels, tutorials, technical papers, and exhibits. The IP Summit will feature a track on IP re-use and integration including a technical panel entitled “Selecting IP in a Complex Design Environment,” chaired by Raghavan Menon, director of engineering, Virage Logic. Panelists include Kalar Rajendiran, senior director of marketing, eSilicon Corporation; Gabriele Saucier, president of Design and Reuse; and Adam Traidman, group marketing director of the chip planning solutions organization at Cadence Design Systems.
- Keynote
Monday, February 2, Noon – 1:00 - CoReUse/QCore — Industries First Design Reuse Methodology with Compliance Checking Tool
Monday, February 2, 1:30 pm – 4:30 pm - Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP
Tuesday, February 3, 8:30 am – 9:10 am - Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design Reusability
Tuesday, February 3, 9:20 am – 10:00 am - Intellectual Property — Fraud Protection
Tuesday, February 3, 10:15 am – 10:55 am - Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers
Tuesday, February 3, 10:15 am – 11:45 am Business Forum Panel - Toward Harnessing the True Potential of IP Reuse
Tuesday, February 3, 11:05 am – 11:45 am - C++ IP Design and Reuse
Tuesday, February 3, 2:00 pm – 2:40 pm - Skeleton, an Approach to Maximize Reuse across Multiple Product Families
Tuesday, February 3, 2:50 pm – 3:30 pm - Selecting IP in a Complex Design Environment
Tuesday, February 3, 3:45 pm – 5:00 pm
More information: DesignCon 2009 Conference and Exhibition
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