Apache Design Solutions to Present at DesignCon
Apache Design Solutions will present at several DesignCon sessions. Apache’s executives will discuss the latest challenges and solutions in maintaining power, noise, and thermal integrity and driving convergence across IC, package, system, and SiP designers. Apache will also demonstrate their power, noise, and reliability platform solutions for Chip-Package-System co-design. Attendees will learn how to mitigate the design risks induced by noise issues, reduce overall cost, and improve productivity and time-to-market.
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Worst-Case Switching Pattern for Core Noise Analysis (4-TA3) Technical Paper
This paper demonstrates an optimum methodology to capture the worst-case switching activity when performing the power integrity analysis for the core power of ASIC
Santa Clara Convention Center, Ballroom J
Tuesday, February 3, 10:15AM to 10:55AM -
Collaboration across the Changing Design Chain Business Forum Panel
This panel will discuss the challenges faced by IC and system designers on reaping the benefits of SiP technology and what foundries and package providers are doing to make SiP a reality
Santa Clara Convention Center, Room 203/204
Tuesday, February 3, 2:00PM to 3:30PM -
Multi-Die Chip/Package Co-Design for SiP Applications Technical Panel
This panel will discuss the challenges faced by the IC and package teams as power, SI, reliability, thermal, stress, etc. issues further exacerbates design and validation of multi-die chips, and the solutions needed to address these challenges
Santa Clara Convention Center, Ballroom G
Tuesday, February 3, 3:45PM to 5:00PM
More info: DesignCon 2009 | Apache Design Solutions
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