Today, the Open Modeling Coalition (OMC) has published a document titled, “Statistical Methods for Semiconductor Chip Design.” The document was developed by the OMC’s Statistical Working Group, and is freely available to the industry. The document is intended to advance the understanding in the industry of statistically based methods and to encourage and support their implementation and use. The publication outlines “best practice” techniques that are being adopted by much of the industry regarding statistical design and how such methods fit into a typical design flow.
Statistical Methods for Semiconductor Chip Design covers statistical techniques needed to ensure the progression of Moore’s law. Lithographic and other process techniques are becoming more and more limited in what can be accomplished from one generation to another. To ensure that scaling can continue to provide the semiconductor industry and its customers the required improvements in performance, better statistically based tools and techniques need to be applied so that design specific requirements can be optimized around technology specific effects.
Statistical Methods for Semiconductor Chip Design
- Need for Statistical Techniques in a Design Flow
- Definitions and Acronyms
- Case Study, Technology Trends & Limitations in Lithography
- Case Study, Statistical STA vs. Conventional STA
- Case Study, Chip Timing and Optimization Using Statistical Analysis Methods
- Intended Usage of Statistical Techniques in a Design Flow
- Design Flow Description, Concept to Reality
- Initial Intent of Specification
- Specification Details
- Physical Variation Effects & Their Approximations
- Mathematical Modeling for SSTA
- Timing Propagation
More info: Statistical Methods for Semiconductor Chip Design (pdf)