Mentor Graphics introduced the Vista Scalable Design Methodology based on a layered transaction level model (TLM). The new methodology enables a single model to be taken from design concept to implementation. The Mentor Graphics Vista family of electronic system level (ESL) design tools are structured to support an efficient “layered” modeling based on the recently announced SystemC Transaction-level Modeling Standard (TLM-2.0) by the Open SystemC Initiative (OSCI).
Using an object-oriented (OO) approach that separates functionality from communication, timing and power, the Vista design suite provides a single-model that can scale from a pure untimed functional model to a fully implemented one. As a result, it seamlessly links with both software domains and hardware implementation for optimized success, efficiency and reliability. This approach applies also for power modeling at the TLM level, for applications such as semiconductors for consumer electronics and mobile communications devices.
An automated, TLM wrapper generation flow between the Catapult C Synthesis tool and Vista now supports TLM-2.0 compatible models. The Catapult-Vista TLM-2.0 model generation flow bridges the gap between hardware design and system-level modeling by providing a link between the Catapult C Synthesis tool untimed ANSI C++ source and the Vista SystemC scalable design and simulation environment. This provides an industry-first automated ESL design flow from high-level synthesis to models based on the TLM-2.0 standard.
More info: Mentor Graphics Vista