The Silicon Integration Initiative (Si2) recently released the Common Power Format (CPF) Version 1.1. The latest release includes major enhancements to the low-power intent format. CPF 1.1 was approved by the Low Power Coalition (LPC). The CPF standard reduces this risk by extending the industry’s RTL-GDSII design infrastructure to support low power design techniques in a safe and efficient manner. In a little over a year the LPC has taken the next step to broaden the applicability to an even larger set of designs and methodologies with CPF 1.1.
CPF is a Tcl-based format used to capture the power intent of a design. CPF complements the RTL and/or netlist description of the design allowing existing golden RTL blocks to be used without modification. CPF has achieved wide acceptance in EDA tools in end-user tool flows, and enjoys a record of numerous completed chip tape-outs with subsequent testimonials, and adoption into leading foundry reference flows.
The extensions in CPF 1.1 further expand support for bottom-up and top-down hierarchical flows and enable the integration, reuse and verification of internal and 3rd party developed power aware IP. Power intent for multiple IP blocks from multiple sources can be integrated together with appropriate resolution of power domains, power modes and power related rules. In addition, CPF 1.1 supports sophisticated macro modeling of hard IP such as embedded memories with complex power structures. This enables implementation and verification of the IP’s power behaviors in the design context.
CPF 1.1 expands the number of power domain operating states to include reversed biased and forward biased states. This enables the support of additional sophisticated power minimization techniques that are becoming more common in low power designs. CPF 1.1 improves the modeling of transitions between power modes which enables in-depth verification to ensure that the design can successfully enter and exit each operating mode, preventing a common source of failure in low power designs. CPF 1.1 also provides a new general model to describe power requirements for special low power cells such as state retention, isolation, “always-on” cells. This improves designer productivity by further automating implementation and verification of the design power intent.
More info: CPF 1.1