Aldec is offering a webinar entitled, Design Rule Checking Tools: a Key to Avoiding ASIC Re-spins. The webcast will take place Wednesday, December 17, 2008 from 11:00 am to 12:00 pm Pacific Standard Time (USA) and 3:00 pm – 4:00 pm Central European Time.
Design rule checking software detects a wide variety of design issues, such as poor coding styles, improper clock and reset management, synthesis problems, poor testability, etc. Recording and detailed analysis of detected issues is facilitated by variety of debugging tools. Implementing corrections suggested by the checking tools leads to faster delivery of better quality ASIC design. This webinar explores the advantages of Design Rule Checking Software with practical live demonstrations of Aldec ALINT solution.
- Typical issues detected in traditional design flow
- Design rule checking
- Rule libraries
- Source-level checking (RTL)
- Connectivity checking
- Netlist-level checking
- Configuring checking process
- Selecting and organizing rules to check
- Fine-tuning rule parameters
- Running checking process
- Analyzing results of checking
- Cross-probing with design sources
- Violation post-processing