SystemVerilog Assertions Language and Methodology Overview Seminar

Aldec is offering a seminar entitled, SystemVerilog Assertions Language and Methodology Overview. The event is targeted at Design Engineers, Verification Engineers, and EDA Tool Managers. The seminar will take place on Tuesday, December 16, 2008 from 10:00 am to 2:00 pm (Pacific Time). The event is free and includes lunch.

System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard. Its hardware oriented concurrent semantics significantly reduce time to develop complex multi-clock domain checkers. Assertions also provide white box observability resulting in a drastic reduction of debug time, further reducing time to production. SVA allows a clean separation of design and verification logic and parameterization of properties resulting in a modular and reusable methodology.


SVA Methodology

  • What’s an assertion? What are the advantages of SVA?
  • Assertion Based Verification (ABV) Methodology Guidelines

SVA Language Overview

  • Immediate assertions
  • Concurrent assertions (with examples and applications)
    • Basics (implication operator, formal args, severity levels, disable iff, etc.)
    • Binding design module to property module
    • Sampled value functions ($rose, $fell, $stable, $past)
    • Operators (clock delay, consecutive, repetition, non-consecutive, goto)
    • Sequence ‘within’, ‘throughout’, ‘and’, ‘intersect’, ‘or’, ‘not’, ‘firstmatch’
    • If…else
    • System Functions ($onehot, $isunknown, etc.)/System Tasks ($asserton, $assertoff, etc.)
    • Multi-Clocked properties
    • Local Variables
    • Embedding concurrent assertions in procedural code; calling subroutines; etc.

The seminar is presented by Ashok Mehta of DefineView Consulting. Mehta has worked in the semiconductor industry for the past 24+ years in hardware design and verification engineering / management positions at companies such as Digital, Data General, Intel, IKOS, Philips Semiconductor, AMCC and many startups. Ashok has been a member of technical sub-committees on IEEE Verilog, SDF, and EIA 576. He brings real life experience as a user of HDL and HVL languages and methodologies to the training class.

Sunnyvale, CA
440 N. Wolfe Rd. – Sunnyvale, CA 94085

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