Cadence Design Systems, Inc. (NASDAQ: CDNS) recently introduced the Encounter Power System, which is a next-generation power integrity and analysis solution for digital implementation and signoff. Encounter Power System provides a unified interface and database for timing, signal integrity, power analysis and diagnostics, enabling correct-by-construction optimization and signoff across these domains. The system was tested on multiple designs and process nodes by leading IC companies including Fujitsu Microelectronics, Ltd., Cortina Systems, SiCortex and Tilera, and those companies reported significantly improved productivity, precision, and performance.
Encounter Power System delivers these benefits by providing a comprehensive view of timing and power integrity in the design phase. The unified database delivers fast, full-chip power grid analysis, as well as enhanced static and dynamic analysis, electromigration, thermal analysis, and statistical analyses, including on-chip power impacts from package and board parasitics.
Encounter Power System provides full-featured, integrated gate- and grid-level power integrity analysis throughout the design flow, including floorplanning, power planning, design, implementation, clock-tree synthesis, signoff and manufacturing, resulting in consistent, correlated, signoff-quality results at every step of the flow.
In combination with Encounter Timing System and Encounter Library Characterizer, Encounter Power System offers integrated timing, SI, power and statistical characterization and analysis with a common user interface, constraints, commands, debug and reporting. With its tight integration to the Encounter digital IC design platform, Encounter Power System can be leveraged for quick what-if analysis, design optimization with decoupling-capacitance and power-switch ECOs, and final signoff, all from within the Encounter interface.
More info: Cadence