Synopsys DesignWare DDR3/2, DDR2/3-Lite, and DDR2/DDR IP

Synopsys, Inc. (NASDAQ: SNPS) recently introduced silicon-proven DesignWare DDR IP solutions for systems-on-chips (SoCs) that require an interface to high-performance DDR3, DDR2 and DDR memory subsystems. The DesignWare DDR IP solutions deliver memory system performance of up to 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. The solutions include configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os and verification IP. The DesignWare DDR IP portfolio provides designers with scalable solutions that help reduce risk and speed time-to-market for applications such as digital home, digital office, data center and storage. The DesignWare DDR3/2, DDR2/3-Lite and DDR2/DDR IP solutions are available now. The DDR PHY IP is available in leading 130nm, 90nm, and 65nm process technologies.

Synopsys DesignWare DDR IP solutionsThe comprehensive DesignWare DDR IP portfolio consists of three product lines including DDR3/2, DDR2/3-Lite and DDR2/DDR, all of which have been validated and fully characterized in Synopsys’ silicon test chips and support two generations of DDR SDRAM:

  • DDR3/2 IP
    Helps satisfy the needs of the highest performance interfaces with operation at up to 1600 Mbps and offers a wealth of in-system calibration capabilities to ease implementation of the interface at higher data rates.
  • DDR2/3-Lite IP
    An area- and feature-optimized IP solution operating at up to 1066 Mbps using DDR2 or DDR3 SDRAMs. The DDR2/3-Lite IP is ideal for SoCs that initially target DDR2 SDRAMs, and has the option of migrating to DDR3 when it becomes more cost effective without the need to modify the current SoC design.
  • DDR2/DDR IP
    Operates at speeds up to 1066 Mbps and is available in leading 130nm, 90nm and 65nm process technologies.

SDRAM Controller Features

  • Implementation choices: lean and efficient DDRn protocol controller core or full-featured multi-port memory controller core with optimized scheduling operation
  • Configurable address and data widths, buffer depths, ECC, memory addressing, pipelines and PHY control
  • Integrated calibration and data training for DesignWare DDRn PHYs
  • Support for native interfaces or AMBA 3 on-chip bus interfaces

PHY Features

  • Fully integrated, hard macro PHY that includes application specific SSTL I/O library
  • DDR3 speed grades up to 1600 Mbps
  • DDR2 speed grades up to 1066 Mbps
  • Modular architecture for flexible placement and flexible I/O ring design

DesignWare Verification IP Features

  • Verifies all configurations of the DDRn Interface including the PHY and memory controller
  • Supports directed and constrained random traffic generation
  • Provides functional coverage of transactions and coverage of the compliance checklist

More info: Synopsys