Synopsys, Inc. (NASDAQ: SNPS) recently introduced fully synthesizable implementations of the IBM PowerPC 460 and cache configurable PowerPC 405 embedded microprocessor cores as components of the DesignWare Star IP program. The PowerPC 460S is a 32-bit high performance, low-power embedded processor core optimized to meet the performance and power requirements of today’s consumer electronics, communications, and storage applications. As a synthesizable version of IBM’s PowerPC 464 hard core, the PowerPC 460S allows the system-on-chip (SoC) designer to select the L2 cache size, L1 cache size, and multi-core processor local bus necessary to optimize their design. Additionally, the PowerPC 460S supports an optional floating point unit.
The PowerPC 405S is a 32-bit low power, mid performance embedded processor core with design attributes that make it an ideal solution for emerging consumer, storage, wired and wireless applications. As a synthesizable version of IBM’s most popular hard core series, the PowerPC 405S now supports a user-definable L1 cache size that helps SoC designers optimize performance and area to match the application requirements.
The PowerPC 460S and 405S processors are distributed as simulation and timing models and synthesizable register transfer level (RTL) cores. Synthesizable IBM CoreConnect peripherals are also available to licensees of the PowerPC cores. The combination of synthesizable PowerPC cores and CoreConnect peripherals with the DesignWare IP portfolio gives designers a comprehensive PowerPC solution spanning all facets of SoC design from system-level design to implementation.
PowerPC 460S and PowerPC 405S design views, including the simulation and timing models, a verification environment, and full documentation are currently available at no additional charge to DesignWare Library customers. For an additional fee, DesignWare Library users may license from IBM or Synopsys the implementation views of the core, including fully synthesizable RTL.