System Verilog Assertions Training
DefineView Consulting is offering a training class for System Verilog Assertions (SVA). The class will take place on November 12, 2008 (9am – 6pm) in San Jose, CA. Each operator/feature is explained in detail using comprehensive examples, timing diagrams and simulation logs. Real life applications are discussed to put it all in perspective. A reference grade handout book is provided to the class. It has comprehensive detail on each page that can serve as excellent reference material for future. Labs are geared to solidify understanding of key concepts using application oriented designs. Class also explains practical ways to deploy SVA into your existing Verilog/System Verilog methodology and delineates real life methodology components that you can apply right away.
[New Date and Price Update: December 4, 2008 (9am – 6pm) and $550 per student.]
The cost is $495 per student (10% discount when 3 or more students attend from the same company).
System Verilog Assertions – Methodology and Language
SVA Methodology Overview
- What’s an assertion? What are the advantages of SVA?
- Assertion Based Verification (ABV) Methodology Guidelines
SVA Language Overview
- Immediate assertions
- Concurrent assertions (/with examples and applications/)
- Basics (implication operator, formal args, severity levels, disable iff, pipelined behavior, threads, etc.)
- Binding design module to property module
- Sampled value functions ($rose, $fell, $stable, $past, performance implications)
- Operators (clock delay, consecutive, non-consecutive, goto)
- Sequence ‘within’, ‘throughout’, ‘and’, ‘intersect’, ‘or’, ‘not’,'firstmatch’
- If…else
- Recursive properties (mutually exclusive, 0 delay loops, restrictions)
- System Functions ($onehot, $isunknown, etc.)/System Tasks ($asserton, $assertoff, etc.)
- Multi-Clocked properties (basic and with ‘and’, ‘or’, ‘not’ operators)
- Local Variables (basics, illegal usage, visibility rules, threads)
- Detecting and using endpoints (.ended, .matched)
- The ‘expect’ and ‘assume’ statements
- Embedding concurrent assertions in procedural code; calling subroutines
- Finer points
- SVA allows only fixed delays. So what if you want variable delays?
- Pros/cons of unbounded ($ infinite) range
Labs
- Learn how to ‘bind’ property; understand vacuous pass with/without implication
- Learn how pipelined threads work
- Model FIFO assertions, Bus protocol assertions
More info: DefineView Consulting
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