The Accellera Board of Directors and Technical Committee members recently approved version 2.3 of its Verilog-Analog Mixed-Signal (AMS) standard. Verilog-AMS is an Accellera standard for analog and mixed-signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364[tm]-2005 or Verilog hardware description language (HDL) standard.
Verilog-AMS 2.3 enables users to develop standard and tightly integrated Verilog-AMS modules and allows EDA software tool developers to implement EDA tools without ambiguities in the language interpretation.
Verilog-AMS 2.3 encompasses analog and mixed-signal extensions to IEEE Std. 1364, which is widely used today for digital circuit design and verification. The previous Accellera Verilog-AMS standard, Verilog-AMS 2.2, was approved in 2005.