IPextreme®, Inc. recently introduced the first synthesizable IP core that implements the upcoming IEEE 1149.7 standard. The cJTAG – IEEE 1149.7 IP core is a configurable, ready-to-integrate semiconductor IP solution supporting all six classes of the IEEE 1149.7 standard. The IEEE 1149.7 test and debug technology will allow the electronics industry to extend IEEE 1149.1 capabilities while also providing increased functionality for embedded designs. The cJTAG – IEEE 1149.7 product includes Verilog source code, integration testbench and tests, documentation and scripts for simulation and synthesis, with support for common EDA tools. cJTAG – IEEE 1149.7 is available for $75K.
IEEE 1149.7 does not change or replace IEEE 1149.1. Instead, it offers a scalable set of extensions to IEEE 1149.1 that ensures interoperability between IEEE 1149.1- and IEEE 1149.7-based devices and test equipment. IEEE 1149.7, which will be ratified in early 2009, will extend the current IEEE 1149.1 (JTAG) standard, uses fewer pins, and maintains compatibility with IEEE 1149.1-based hardware and software.
cJTAG – IEEE 1149.7 Features
- Support for IEEE 1149.7 classes 0-5 (selected through hardware configuration parameter)
- Partitioned along IEEE 1149.7-specified functional boundaries:
- Extended processing unit (EPU) for class 0-3 operation
- Advanced processing unit (APU) for class 4-5 operation
- Further parameterization within EPU and APU for class-specific and optional features
- Separate blocks for clock and reset signal conditioning
- Supports all mandatory and optional scan formats: JScan0-3, SScan0-3, OScan0-7 and MScan
- Supports all mandatory and optional commands
- Firewall provides robust hot-connection by disabling test clock (TCK) until firewall is disabled by the debug test system (DTS)
More info: cJTAG – IEEE 1149.7