The C-to-Silicon Compiler, from Cadence Design Systems, Inc. (NASDAQ: CDNS), is a high-level synthesis product that improves designer productivity up to 10 times in creating and re-using system-on-chip IP. The C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models and system-level models, usually written in C/C++ and SystemC. The Cadence C-to-Silicon Compiler is available now.
C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. Designer productivity is improved because the technology automatically translates and optimizes abstract behavioral descriptions from C/C++ and SystemC to synthesizeable Verilog RTL (including assertions) for implementation, verification and SoC integration.
C-to-Silicon Compiler has two very distinctive capabilities: embedded logic synthesis using Cadence Encounter RTL Compiler global synthesis that ensures high accuracy and high-quality implementation results for designs with mixed control and datapath, and a behavior-structure-timing database that provides the ability to perform true incremental synthesis, for example re-synthesizing only the parts of the design that changed, while leaving the rest untouched. Finally, to support verification, C-to-Silicon Compiler generates fast cycle-accurate hardware models of the RTL, and supports fast mapping to RTL verification with Incisive simulation and Palladium/Xtreme emulation-acceleration products.
More info: Cadence