Design and Test Challenges for 3D ICs Workshop

The SEMATECH workshop, “Design and Test Challenges for 3D ICs,” will be held in conjunction with the IEEE/ACM 2008 International Conference on Computer-Aided Design on November 13 in San Jose, California. The workshop will benefit IC manufacturers, electronic design automation (EDA) professionals, product engineers and designers, test engineers, researchers and managers involved in the development and/or implementation of 3D TSV technology.

SEMATECH’s 3D program encompasses equipment evaluations, unit processes, integration and metrology. The day-long workshop will conclude with a panel discussion on how the EDA industry is responding to TSVs, which will feature experts from leading commercial semiconductor and EDA companies. The panel will explore whether the design needs for stacked die systems represent an evolution or a discontinuity for the EDA industry, and will examine these alternatives by looking at EDA vendor strategies and the needs of design teams involved in TSV-based systems.

SEMATECH Workshop Speakers

  • 3D Market Overview, Jan Vardaman, TechSearch
  • The Challenges of Design and Test of the 80 Core Chip, Tanay Karnik, Intel
  • 3D Integration – Opportunities and Challenges, Koushik Das, IBM Research
  • Reliable Power Delivery for 3D Integrated Circuits, Sachin S. Sapatnekar, University of Minnesota
  • Thermal Challenges and Solutions for 3D ICs, Edmund Cheng, Gradient
  • Cost Analysis and Design Exploration for 3D ICs, Yuan Xie, Penn State University
  • Memory Rich Application Exploration for 3D Integration, Paul Franzon, North Carolina State University
  • 3D-DRAM Circuit Design, Modeling and Exploration for Computer Memory Hierarchy, Tong Zhang, RPI
  • Test and Design for Test of 3D ICs, Prasad Mantri, SUN
  • Testing Options for 3D devices that use Through Silicon Stacking, Michael Laisne, Qualcomm

More info: SEMATECH Design and Test Challenges for 3D ICs