Evatronix SA recently introduced the T8051 IP Core, which is the smallest microcontroller that implements Intel 8051 Instruction Set Architecture. The design has one of the best performance-to-size ratios on the market. The T8051 IP core is available for licensing now. Standard deliverables include various sets of scripts for trouble-free synthesis and simulation as well as an extensive Verilog 2001 testbench, while the proprietary prototyping environment can be purchased as an option.
With the CPU’s 2700 gates, the T8051 is ideal for IC designers who want to make use of complete 8-bit architecture functionality while substantially reducing the size of their systems. The lowest possible gate count is especially valuable for engineers working with mixed signal designs implemented in older processes with larger feature sizes, where the silicon area is a significant factor.
The T8051 makes it possible to replace hard-coded control FSM with a programmable microcontroller, which was hard to reach with a significant difference in gate count between the two solutions.
Despite its tiny size, the T8051 is a powerful 8-bit microcontroller. Instruction cycle latency has been tuned to minimize hardware resources, however, the core still performs 4.1 times better than the original Intel 8051 in terms of Dhrystone MIPS per MHz. Communication with both built-in and external memories has been accelerated by de-multiplexing the address and data buses, while alternate port functions such as external interrupts and serial interface are available on separate pins – all this to give the user a possibility to connect and effectively manage a greater number of peripheral devices.
More info: Evatronix