SynaptiCAD recently released a new version of its V2V tools for translating between VHDL and Verilog source code that supports Verilog 2001 code constructs. In addition, SynaptiCAD’s BugHunter Pro can now be used as a graphical debugging environment for translating and testing the new models. The V2V translator software is available on Windows and Linux. The software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.
New features in the core translators include support for Verilog 2001 style “port” and “signal” declarations, plus support for the Verilog 2001 “signed” keyword. The tool is also now able to translate code automatically in several cases that previously required manually pre-editing for a successful translation.
The typical translation design flow involves an iterative cycle where the user must make some manual changes to either the original or the generated code. To speed up this flow, SynaptiCAD has introduced an optional graphical debugging front-end based on its BugHunter Pro HDL Debugger tool. With BugHunter, users can launch the translators via point-and-click mouse operations, set options to the translators via a dialog window, and double click on errors and warnings generated during translation to launch a text editor and make changes at the problematic lines in the source code.
BugHunter can also launch VHDL and Verilog simulators on both the original and the translated code, dramatically speeding up the process of verifying and modifying the translated code. The environment allows users to create language independent test benches that simplify verifying that the translated code matches the functionality of the original code. BugHunter also supports full single-step debugging, waveform capture, and variable inspection with the following simulators: SynaptiCAD’s VeriLogger Extreme, Cadence’s Incisive, Synopsys’ VCS, Mentor Graphic’s ModelSim, and Aldec’s ActiveHDL.
More info: SynaptiCAD