STMicroelectronics ESL SoC Reference Design Flow

STMicroelectronics (NYSE: STM) recently announced a certified electronic system level (ESL) System-on-Chip reference design flow. Aimed at complex designs for next-generation consumer electronics equipment, ST’s integrated ESL reference-design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a complete methodology from ANSI C++ to RTL including certified integration ST’s certified RTL-to-GDS2 design flow. As a result, hardware designers using ST’s ESL reference flow are able to create and verify chips faster, with higher quality.

The ST design flow is integrated with Atrenta’s industry-standard SpyGlass® for RTL lint checking and power analysis; the Mentor Graphics® Catapult® C Synthesis tool; and Calypto Design Systems’ SLEC equivalence checker, providing highly efficient synthesis from pure ANSI C++ to RTL and formally verifying that the resulting RTL implementation is functionally correct. The advanced flow provides a comprehensive solution that includes: RTL lint sign-off; power estimation and exploration; C-to-C formal equivalence checking; C-to-RTL formal equivalence checking; SystemC model generation; and C-to-RTL high-level synthesis, thereby minimizing risk and shortening design cycles with ‘real-world’ productivity gains of between four and ten times.

More info: STMicroelectronics