Gap-Free RTL Verification with SystemVerilog Assertions

OneSpin Solutions recently introduced the first verification solution that features gap-free RTL verification using SystemVerilog Assertions (SVA). The solution leverages a new, SVA Timing Diagram Assertion Library, TIDAL, that helps users easily capture timing diagrams as SVA properties. Users of OneSpin’s 360 Module Verifier (360 MV) now can employ SVA to implement the GapFreeVerification process that slashes verification effort and ensures highest possible verification quality. SVA-based GapFreeVerification and TIDAL are included at no extra charge in version 5.0 of 360 MV.

GapFreeVerification is the only closed-loop verification process using SVA. It guides users in verification planning, execution, debug and formal coverage analysis. Automatic gap detection identifies unverified RTL functionality as well as gaps and errors in the specification. As a result, it greatly simplifies verification planning, and eliminates the need to construct coverage models and manually analyze extensive coverage data to assess and improve verification quality. 360 MV’s automatic gap detection also is the first technology to enable integration of verification planning, execution and verification quality analysis into a closed-loop process – the key to higher productivity and highest quality in verification.

TIDAL supports 360 MV’s intuitive operation-based verification approach. It enables users to directly transcribe timing diagrams that specify the intended behavior of module-level operations into corresponding SVA properties. Users then can employ 360 MV’s automatic gap-detection to systematically find and close all gaps in the SVA property set. TIDAL’s constructs, modeled in standard SVA, allow users to leverage the familiar concept of timing diagrams for formal verification, speeding learning and adoption by novices and formal experts.

More info: OneSpin Solutions