Beyond Vendor Supplied Verification Tools Webinar

Posted by Ken Cheung in Events, Training on Tuesday, September 2, 2008
DVCon Issues Call for Papers, Panels, and Tutorials »
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Aldec is offering a webinar titled, Beyond Vendor Supplied Verification Tools. The webcast will take place Thursday, September 25 at 3:00 PM Central European Summer Time (CEST). Jaroslaw Kaczynski, Technical Marketing Engineer, will be the presenter.

Agenda

  • Vendor independent design management
  • Advanced text and graphical design entry
  • High-performance simulation
  • State-of-the-art debugging tools
  • Automated design documentation

Abstract

Vendor-supplied FPGA development tools are inexpensive (sometimes free) and in some areas (e.g. implementation or place & route) indispensable. When you have to deal with advanced methods of design entry and management or perform lengthy simulation of large circuits, they provide only basic functionality. If you have to work with more than one FPGA vendor, using their tools also means switching between totally different environments when you switch vendors. You can get better results faster (and in more comfortable environment) by using independent design entry, management and simulation tools.

More info: Beyond Vendor Supplied Verification Tools

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DVCon Issues Call for Papers, Panels, and Tutorials »
« Training: SystemVerilog Assertions and Functional Coverage

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