Training: SystemVerilog Assertions and Functional Coverage

Aldec is offering a training class on SystemVerilog Assertions and Functional Coverage; Methodology & Language. The training will take place from 9:00 am to 5:00 pm on Monday and Tuesday, September 15th and 16th in Santa Clara Network Meeting Center. The two-day course costs $1200.

Training Class Highlights

  • Each operator/feature is explained in detail using simple examples, timing diagrams and simulation logs
  • Real life applications are discussed to put it all in perspective
  • A 250+ page handout book is provided to the class. It has comprehensive detail on each page that can serve as excellent reference material for future
  • Labs are geared to solidify understanding of key concepts using application oriented easy to use designs
  • Class also explains practical ways to deploy SVA into your existing Verilog/System Verilog methodology and delineates real life methodology components that you can apply right away

Day 1

Introduction to Assertions

  • What’s an assertion? Why can’t I just use Verilog? SVA advantages over Verilog
  • Advantages of Assertion Based Verification (ABV)
  • Assertion Based Verification (ABV) Methodology components
  • Who writes them? What types of assertions do you write? etc.

System Verilog Assertions :: Syntax and Semantics

  • Immediate assertions
  • Concurrent assertions – Basics
  • clocking basics; formal arguments; severity levels; threads
  • Sequence introduction
  • Property introduction (with/without an implication)
  • Vacuous pass?
  • Binding properties
  • Threading

LAB 1: Understand vacuous pass and results with/without implication

LAB 2: Enforces how pipelined threads of a property work

  • Sampled value functions (in property/sequence and procedural)
  • Functions that return boolean pass/fail: $rose, $fell, $stable
  • Function that return sampled value; $past (with/without gating expr.)
  • Sequence Operators
  • ##m and ##[m:n] clock delay (SVA allows only fixed delays. So what if you want variable delays??)
  • [* ] and [*m:n] – Consecutive repetition operator
  • [= ] and [=m:n] – Non-consecutive repetition operator
  • [-> ] and [-> m:n] – Goto (non-consecutive) repetition operator
  • Pros/Cons of infinite ($) range
  • ‘throughout’, ‘within’, ‘and’, ‘intersect’, ‘or’, ‘first_match’
  • ‘intersect’ vs. ‘and’

LAB 3: FIFO

  • A simple FIFO design is presented. You will code different properties to meet various FIFO fail conditions.
  • FIFO assertions are some of the most useful assertions to code for any design. This lab teaches how to do that so that you can apply them directly to your design.

Day 2

  • Property operators
  • ‘not’ operator
  • If … else
  • ‘disable iff’
  • Recursive property
  • Mutually exclusive
  • 0 delay infinite loop
  • Restrictions
  • System functions
  • $onehot, $onehot0, $isunknown, $countones
  • Multiple Clocks
  • Multiply clocked sequences and properties – legal and Illegal usage
  • Multiply clocked properties and ‘and’, ‘or’, ‘not’ operator
  • Multiply clocked properties – Clock resolutions
  • Local variables (one of the most powerful features…)
  • Basics and Visibility rules, legal and illegal usage
  • Pipelined behavior (threads)
  • Special consideration for ‘and’ and ‘or’ Detecting and using endpoint of a sequence
  • .ended, .matched
  • The ‘expect’ statement, ‘assume’ statement
  • Embedding concurrent assertions in procedural code
  • Calling subroutines
  • Asynchronous Assertions
  • Multiple implications in a property; blocking action_blocks

LAB 4: COUNTER Assertions

  • Code different properties to meet various Counter fail conditions
  • Enforces the use of Local Variables, $past system task, etc.

LAB 5: BUS PROTOCOL Assertions

  • Code different properties to meet bus protocol fail conditions
  • Exemplifies temporal domain assertions coding ($stable, $rose, throughout, etc.)
  • Shows two different ways to code the same property

System Verilog Functional Coverage

  • Code coverage vs. Functional coverage
  • Features
  • ‘covergroup’
  • ‘coverpoint’
  • ‘bins’
  • ‘cross’ coverage
  • Transition coverage
  • Wildcard bins
  • ‘ignore_bins’ and ‘illegal_bins’
  • ‘binsof’ ‘intersect’
  • Coverage options
  • Instance specific
  • ‘covergroup’ type
  • System tasks for coverage
  • Coverage methods for use in procedural code

More info: SystemVerilog Assertions and Functional Coverage; Methodology & Language Training Class