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Synopsys HAPS-51T High-performance ASIC Prototyping System

Posted by Ken Cheung in EDA Tools on Wednesday, August 27, 2008

The HAPS-51T, from Synopsys, Inc. (NASDAQ: SNPS), leverages the advanced capabilities of Xilinx’s Virtex-5 LX330T devices. The new HAPS (High-performance ASIC Prototyping System) product is an ideal prototyping system for applications using high-speed serial interfaces like PCI Express, SATA and Gigabit Ethernet. The HAPS-51T utilizes the LX330T device’s 24 RocketIO GTP transceivers, adding on-board DDR2 memory and the new HapsTrak high-speed daughterboard connectivity scheme in a compact form factor. These features enable HAPS-51T to deliver a significant advantage in performance and versatility.

The tight connection between the Virtex-5 LX330T FPGA and the on-board memory enables flexible, high-speed memory access to satisfy even demanding communication applications. The HAPS-51T is equipped with programmable clock generators, sophisticated monitoring and self-test features, as well as remote configuration and setup capabilities.

The easily expandable, modular architecture of Synopsys’ HAPS systems offer many sophisticated features designed to appeal to system-on-chip (SoC) designers and software engineers alike. The HAPS-51T utilizes the HapsTrak standard, a set of guidelines for pinout and mechanical characteristics to help ensure compatibility with previous and future generations of HAPS motherboards and daughterboards. In addition, the HAPS-51T introduces the new HapsTrak MGB multi-gigabit SERDES bus with up to 8 lanes.

HAPS-51T’s On-board Memory

  • 1GByte of DDR2, expandable to 8GByte
  • 2Mbit x 36bit synchronous SRAM
  • 32Mbit x 16bit Flash PROM

MGB Daughter Board Support

  • PCIE-4_MGB: 4-lane PCI Express
  • SATA-4_MGB: 4-channel serial ATA
  • ETH-4_MGB: 4 Gbit Ethernet ports

Integrated Peripherals

  • USB data port
  • SelectMAP
  • JTAG

More info: High-performance ASIC Prototyping System

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