DDR PHY Interface Specification 2.0

Version 2.0 of the DFI specification was recently released. The collaborative technical working group delivered several improvements and enhancements in this latest version of the DFI specification. This version of the specification extends support to include DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. Chip architects, memory controller vendors, and PHY providers can utilize the new specification to speed their DDR memory system design and integration, and reduces the significant verification costs.

The DFI specification 2.0 is available through a click-thru license. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP.

More info: DFI Specification