Aldec is offering a seminar titled, “SystemVerilog Assertions and Functional Coverage.” The event will take place on Thursday, August 21st. Two sessions are available: (1) Morning: 8am to noon and (2) Afternoon: 1:00 pm to 5:00 pm. The cost is $199. Continental breakfast or refreshments are included. The seminar will be presented by Ashok Mehta of DefineView Consulting. Mehta has worked in the semiconductor industry for the past 24+ years in hardware design and verification engineering / management positions.
- What’s an assertion?
- What are the advantages of SVA?
- Assertion Based Verification (ABV) Methodology Guidelines
SVA Language Overview
- Immediate assertions
- Concurrent assertions
- Basics (implication operator, formal args, severity levels, disable iff, etc.)
- Binding design module to property module
- Sampled value functions ($rose, $fell, $stable, $past)
- Operators (clock delay, consecutive, repetition, non-consecutive, goto)
- Sequence ‘within’, ‘throughout’, ‘and’, ‘intersect’, ‘or’, ‘not’, ‘firstmatch’
- If… else
- System Functions ($onehot, $isunknown, etc.)/System Tasks ($asserton, $assertoff, etc.)
- .ended, .matched methods to detect endpoint of a sequence
- Multi-Clocked properties
- Local Variables
- Recursive properties
- embedding concurrent assertions in procedural code; calling subroutines; etc
Functional Coverage Overview
- Code Coverage vs. Functional Coverage
- Brief overview of covergroup, coverpoint, cross, transition with simple applications
System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard. Its hardware oriented concurrent semantics allow for intuitive development of complex multi-clock domain checkers to catch those elusive bugs at the source. It allows for clean separation from the design logic and allows for parameterization of properties resulting in a modular reusable methodology.
Functional Coverage (FC) is another subset of System Verilog that allows you to measure how much of design intent have you covered with your tests/regressions. Combined SVA and FC allow for a modular, reusable and objective methodology that shortens time to develop and debug and gain much higher confidence in delivering a first pass working silicon.