Best Practices for Quick Closure of Verilog Designs

Aldec will be presenting a seminar at 11 am (Pacific Daylight Time) on Thursday, August 14, 2008. When you design ASIC you have to deal with the tangled reset circuits, multiple clock domain circuits, power dissipation, and other complex issues. In this presentation we will discuss the best design practices for the proper reset circuit, avoiding glitches in cross domain data paths, special consideration for using gated clocks in your design, and some coding techniques for the most efficient verification of the design. Following these practices insures the absence of hard to find bugs later in the design process and eventually help avoiding costly ASIC re-spins.

Agenda

  • Designing the reset circuit that can propagate to all flip flops of the system
  • Avoiding meta-stability in multiple clock domain data paths
  • Special considerations for using gated clocks
  • DFT considerations
  • Verification techniques

More info: AVMS VI-05: Best Practices for Quick Closure of Verilog Designs