Berkeley Design Automation, Inc. recently announced the availability of Noise Analysis Option for complex analog and RF circuits. The tool handles every type of complex analog and RF circuit, including all analog-to-digital converters (ADCs), phase-locked loops (PLLs), DC:DC converters, frequency synthesizers, and voltage-controlled oscillators (VCOs). The Noise Analysis Option is fully compatible with existing flows, produces true SPICE accurate results, and is already silicon proven.
Device noise is insidious to GHz nanometer-scale analog and RF CMOS circuit performance. Until now, it has been either impractical or impossible to perform transistor-level analysis of the impact of device noise for many complex analog and RF circuits including sigma-delta ADCs, video DACs, fractional-N PLLs, frequency synthesizers, and wideband VCOs. Design teams have had to rely on hand calculations, system-level models, or costly silicon measurements.
The tool reads standard Cadence Spectre® and Synopsys HSPICE® netlists and models. It is fully integrated into Cadence Virtuoso Analog Design Environment and can operate from a command line. It produces standard output formats and includes sophisticated post-processing.
Noise Analysis Option Features
- Transient-noise analysis 5x-10x faster and 5x-10x higher capacity than any other tool
- Periodic steady-state (PSS) convergence with up to 50,000 element capacity
- Periodic noise (pnoise) analysis that has no accuracy/performance tradeoff and is 5x-10x faster than any other tool for complex circuits
- Oscillator phase noise (oscnoise) analysis that delivers unmatched accuracy on autonomous circuits, provides node and device noise contribution, and automatically provides impulse sensitivity function (ISF) information for every node
More info: Berkeley Design Automation