Preview of VHDL 4.0

Aldec will be presenting a seminar at 11am (Pacific Daylight Time) on Thursday, July 24, 2008. Aldec will give an overview of the most important extensions to VHDL 4.0 approved by Accelera committee for IEEE balloting in 2008, as the part of forthcoming IEEE standard 1076 revision. All new features maintain backwards compatibility to ensure that old designs work without changes, but allow faster creation of better quality new code.

Agenda

  • Merging of several closely related standards (e.g. IEEE Std 1164) into the main VHDL standard
  • Unification and extension of the signal assignment statements
  • Improved existing and added new operators
  • Enhanced generate statements
  • Inclusion of PSL simple subset and VHPI
  • New fixed-point arithmetic packages
  • Support for IP encryption

More info: AVMSVI-03 – Preview of VHDL 4.0